1. Field of the Invention
The invention relates to the field of microelectronics fabrications. More particularly, the invention relates to the field of microelectronics fabrications employing low power field effect transistor (FET) devices.
2. Description of the Related Art
Microelectronics fabrications may combine various kinds of electronic devices and components within their design. One of the most important kinds of electronic device encountered in modern microelectronics is the field effect transistor (FET), which employs a gate electrode insulated from a conductive channel formed between source and drain electrode regions. In one type of FET commonly employed in modern microelectronics fabrications, the source and drain electrode regions may be fabricated by forming n-type regions in a p-type silicon substrate to form n-type metal oxide silicon field effect transistor (NMOSFET). When fabricated with light n-type doping in the drain region, the n-type lightly doped drain (nLDD) device is commonly employed in integrated circuit microelectronics fabrications where low power dissipation is desired. The complementary type of FET is the pMOS device which employs p-type doped regions for source and drain in an n-type substrate. The pMOS device has somewhat lower current drive capability compared to the nMOS device, but has inherently lower drain leakage current.
Conventional FET device designs are often embellished with doped regions additional to the source and drain regions. Such regions are often formed adjacent to source and/or drain regions by ion implantation, and serve to modify or improve device characteristics. These additional doped regions are referred to as pocket regions, and may be either polarity depending on the particular device and purpose.
For many applications in microelectronics technology where drive current capability with low power dissipation is important, it is desirable to have an nMOS FET with very low drain leakage current. Methods of formation of drain junctions which have low reverse-bias current accomplish this objective, either by the inherent nature of the junction or by utilizing a compensating method such as a pocket region surrounding the drain region. Formation of pocket regions with conventional p-type dopants such as boron are not without problems, such as reverse short channel effects (RSCE), which limit the operation of the FET.
It is thus towards the goal of forming nLDD NMOSFET devices with low drain leakage current and power consumption and reduced reverse short channel effect that the present invention is particularly directed.
Various methods have been disclosed for forming pocket regions adjacent to source or drain regions in a FET device to modify device properties.
For example, Burr et al., in U.S. Pat. NO. 5,753,958, disclose a method for forming a FET with adjustable threshold voltage by employing a pocket region adjacent to source or drain of an FET to adjust the threshold voltage of the FET device. The method employs a voltage applied directly to the pocket region by means of a connection line thereto, and there may be applied a back bias to the device by the same means.
Further, Burr et al., in U.S. Pat. No. 5,780.912, disclose a method for forming a low threshold voltage FET device having an asymmetric threshold voltage. The method employs an implanted halo pocket region under and adjacent to source or drain region of the FET device.
Still further, Tsai et al., in U.S. Pat. No. 5,757,045, disclose a CMOS structure for forming a CMOS FET device with reduced susceptibility to punch-through. The structure employs a dual pocket regions implanted in the channel regions adjacent to source and drain regions.
Finally, Richards, Jr. et al., in U.S. Pat. No. 5,786,620, disclose a method for forming a Fermi-threshold FET device with significantly improved threshold voltage and performance. The method employs an implanted pocket region adjacent to the drain region of opposite conductivity type, which acts as a stop to the drain electric field and prevents drain--source reach-through, increasing short channel performance.
Desirable in the art of FET devices formed within microelectronics fabrications are additional methods for forming FET devices with low drain leakage current and low power consumption.
It is towards these goals that the present invention is generally directed.